A 9-Bit, 200MS/s Low Power CMOS Pipeline ADC
نویسندگان
چکیده
This paper describes 9-bit, 200MS/s Pipeline analog to digital converter implemented in 0.18μm CMOS process consuming 48.97mW power from 1.8v supply. To improve the linearity of pipeline ADC is designed which has three stages, 3-bit/stage architecture. Operational transcconductance amplifier is adopted in all pipeline stage to give good power efficiency. The converter is optimized for low voltage, low power application by optimizing opamp and 3bit flash at circuit level.
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